The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Plasma etching is frequently used in semiconductor fabrication. In plasma etching, ions are accelerated by an electric field to etch exposed surfaces on a substrate. The electric field is generated based on RF power signals generated by a radio frequency (RF) generator of a RF power system. The RF power signals generated by the RF generator must be precisely controlled to effectively execute plasma etching.
A RF power system may include a RF generator, a matching network and a load (e.g., a plasma chamber). The RF generator generates RF power signals, which are received at the matching network. The matching network matches an input impedance of the matching network to a characteristic impedance of a transmission line between the RF generator and the matching network. This impedance matching aids in maximizing an amount of power forwarded to the matching network (“forward power”) and minimizing an amount of power reflected back from the matching network to the RF generator (“reverse power”). Forward power may be maximized and reverse power may be minimized when the input impedance of the matching network matches the characteristic impedance of the transmission line.
An RF matching network may include a load capacitance and a tune capacitance. The load capacitance is connected in parallel with a load (e.g., plasma chamber) and the tune capacitance is connected in series between an RF input and the load. The load capacitance and/or the tune capacitance may include a switching network. The switching network typically includes field effect transistors (FETs) and/or p-type intrinsic n-type (PIN) diodes. A PIN diode has a binary state (i.e. either ON or OFF).
A switching network including FETs and/or PIN diodes is complex due to the number of diodes required. PIN diodes are susceptible to breakdown and are relatively expensive. Switching of the PIN diodes to vary the overall capacitance of a load capacitance or a tune capacitance is performed in a discontinuous fashion. Switching of PIN diodes can cause discontinuous jumps in a resonant frequency and impedance of a matching network, which can be seen by a RF source providing an RF signal to an input of the matching network. In addition, switching of the PIN diodes can cause off resonance operation of the RF source while the resonant frequency is re-established by a feedback control loop. Off-resonance operation can cause significant stress on the FETs. To reduce the stated problems requires, for example, the FETs have an associated capacitor and driving circuit.
Various challenges exist with switching PIN diodes. A capacitance associated with a PIN diode is switched into a circuit by applying a bias voltage across the PIN diode. FIG. 1 shows an example schematic diagram of a traditional dual-pin diode circuit 10 of an impedance matching circuit. The dual-PIN diode circuit 10 includes PIN diodes 14, 16 and corresponding capacitors Cn1, Cn2. The PIN diodes 14, 16 are connected in series respectively with the capacitors Cn1, Cn2 between an RF input terminal 18 and an RF output terminal 20. The PIN diodes 14, 16 receive respectively bias voltages VSWT1, VSWT2.
When one or more of the PIN diodes 14, 16 are forward biased, the dual-PIN diode circuit 10 is in conduction mode and current is permitted to flow between the terminals 18, 20. As a result, the capacitors Cn1, Cn2 are applied to the impedance matching circuit. Conversely, when the PIN diodes are reverse biased, current flow is prevented and in this open-circuit condition, the capacitors Cn1, Cn2 are removed from the impedance matching circuit. As an alternative to using PIN diodes, FET switches can be used. In a FET switch implementation, each individual diode performs as a binary switch having an ON (or conduction) state and an OFF (or open) state. An impedance matching network may include a network of PIN diodes to switch a set of capacitors to cover a capacitance range necessary to cover an impedance space associated with a process range of a reactor (or plasma chamber).